1. Technical Field
The present invention relates to a ferroelectric random access memory device, a display drive integrated circuit, and an electronic apparatus.
2. Related Art
Ferroelectric random access memory (FeRAM) devices, which store information by utilizing the hysteresis found between the polarization and electric field of ferroelectric material, have been drawing attention because of their high-speed operation, low power consumption and non-volatility.
These ferroelectric random access memory devices, as with other memory devices, have the constant problem of memory cell integration density improvement, or size reduction.
For example, JP-A-2002-170935 describes a ferroelectric random access memory device in which active regions connected to a predetermined bit line are arranged in a line along the bit line, and it discloses a technique to reduce the ferroelectric memory cell area through ingenuity in the shape or arrangement of plate lines, word lines and active regions.
However, conventional ferroelectric random access memory devices like the above have a problem in that they have long bit lines, i.e., are long in the direction the bit lines extend, and as a result, the size of the ferroelectric random access memory will be large in that direction.
Meanwhile, various electronic apparatuses have been employing the aforementioned ferroelectric random access memory because of its high-speed operation, low power consumption, and non-volatility. Thus, for example, in a display drive integrated circuit (IC) used in a display apparatus, as detailed later, a larger wiring spacing than that set forth in ordinary design rules (e.g., minimum wiring spacing) may be set in relation to the connection with the display, etc.
Therefore, in addition to the integration density improvement or size reduction of ferroelectric random access memory devices, it is also necessary to improve the integration density of memory cells while conforming to a permitted wiring spacing.